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CY2SSTU32864
1.8V, 25-bit (1:1) or 14-bit (1:2) JEDEC-Compliant Data Register
Features
* Operating frequency: DC to 500 MHz * Supports DDRII SDRAM * Two operations modes: 25 bit (1:1) and 14 bit (1:2) * 1.8V operation * Fully JEDEC-compliant (JESD82-7A) * 96-ball FBGA The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS# and CSR# inputs are high. If either DCS# or CSR# input is low, the Qn outputs will function normally. The RESET input has priority over the DCS# and CSR# control and will force the outputs low. If the DCS#-control functionality is not desired, the CSR# input can be hardwired to ground, in which case the set-up time requirement for DCS# would be the same as for the other D data inputs. The device supports low-power standby operation. When the reset input (RESET#) is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET# is low, all registers are reset and all outputs are forced low. The LVCMOS RESET# and Cn inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the low state during power-up. In the DDR-II RDIMM application, RESET# is specified to be completely asynchronous with respect to CK and CK#. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers.
Functional Description
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR-II DIMM load. The CY2SSTU32864 operates from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 = 1 and C1 = 0 is not allowed and it will default to the C0 = C1 = 0 state.
Pin Configurations
A B C D E F G H J K L M N P R T 1 DCKE D2 D3 DODT D5 D6 NC CK CK# D8 D9 D10 D11 D12 D13 D14 1 2 NC D15 D16 NC D17 D18 RST# DCS# CSR# D19 D20 D21 D22 D23 D24 D25 2 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 3 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 4 5 QCKE Q2 Q3 QODT Q5 Q6 C1 QCS# ZOH Q8 Q9 Q10 Q11 Q12 Q13 Q14 5 6 NC Q15 Q16 NC Q17 Q18 C0 NC ZOL Q19 Q20 Q21 Q22 Q23 Q24 Q25 6 A B C D E F G H J K L M N P R T 1 DCKE D2 D3 DODT D5 D6 NC CK CK# D8 D9 D10 D11 D12 D13 D14 1 2 NC NC NC NC NC NC RST# DCS# CSR# NC NC NC NC NC NC NC 2 3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 3 4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 4 5 QCKEA Q2A Q3A QODTA Q5A Q6A C1 QCSA# ZOH Q8A Q9A Q10A Q11A Q12A Q13A Q14A 5 6 QCKEB Q2B Q3B QODTB Q5B Q6B C0 QCSB# ZOL Q8B Q9B Q10B Q11B Q12B Q13B Q14B 6
A B C D E F G H J K L M N P R T
1 D1 D2 D3 D4 D5 D6 NC CK CK# D8 D9 D10 DODT
2 NC NC NC NC NC NC RST# DCS# CSR# NC NC NC NC
3 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF 3
4 VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD 4
5 Q1A Q2A Q3A Q4A Q5A Q6A C1 QCSA# ZOH Q8A Q9A Q10A QODTA
6 Q1B Q2B Q3B Q4B Q5B Q6B C0 QCSB# ZOL Q8B Q9B Q10B QODTB
D12 NC D13 NC DCKE NC 1 2
Q12A Q12B Q13A Q13B QCKEA QCKEB 5 6
1:1 Register C0 = 0, C1 = 0
1:2 Register A C0 = 0, C1 = 1
1:2 Register B C0 = 1, C1 = 1
Rev 1.0, November 25, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 9
www.SpectraLinear.com
CY2SSTU32864
Pin Definitions
Pin Name GND Pin Number (C0 = 0, C1 = 0) Pin Number (C0 = 0, C1 = 1) Pin Number (C0 = 1, C1 = 1) Description
B3, B4, D3, D4, F3, F4, B3, B4, D3, D4, F3, B3, B4, D3, D4, F3, Ground H3, H4, K3, K4, M3, M4, F4, H3, H4, K3, K4, F4, H3, H4, K3, K4, P3, P4 M3, M4, P3, P4 M3, M4, P3, P4 A4, C3, C4, E3, E4, G3, A4, C3, C4, E3, G4, J3, J4, L3, L4, N3, E4, G3, G4, J3, J4, L3, L4, N3, N4, R3, N4, R3, R4, T4 R4, T4 A3, T3 J5 J6 H1 J1 G6 G5 G2 A3, T3 J5 J6 H1 J1 G6 G5 G2 A4, C3, C4, E3, Power Supply Voltage E4, G3, G4, J3, J4, L3, L4, N3, N4, R3, R4, T4 A3, T3 J5 J6 H1 J1 G6 G5 G2 Input Reference Voltage Reserved Reserved Positive Master Clock Negative Master Clock Configuration Control Input Configuration Control Input Asynchronous Reset - resets registers and disables Vref data and clock differential input receivers Chip Select - Disables D1-D24 when both CSR# and DCS# are High (VDD) Chip Select - Disables D1-D24 when both CSR# and DCS# are High (VDD) Data Input - clocked in on the crossing points of CK and CK# Data Input - clocked in on the crossing points of CK and CK# Data Input - clocked in on the crossing points of CK and CK#
VDD
VREF ZOH ZOL CK CK# C0 C1 RESET#
CSR# DCS# D1 D2-3 D4 D5, 6, 8, 9, 10 D11 D12, 13 D14 D15-25 DODT DCKE Q1A Q2A-3A Q4A
J2 H2
J2 H2
J2 H2 A1
B1, C1
B1, C1
B1, C1 D1
E1, F1, K1, L1, M1 N1 P1, R1 T1 B2, C2, E2, F2, K2, L2, M2, N2, P2, R2, T2 D1 A1
E1, F1, K1, L1, M1 E1, F1, K1, L1, M1 Data Input - clocked in on the crossing points of CK and CK# N1 P1, R1 T1 P1, R1 Data Input - clocked in on the crossing points of CK and CK# Data Input - clocked in on the crossing points of CK and CK# Data Input - clocked in on the crossing points of CK and CK# Data Input - clocked in on the crossing points of CK and CK# D1 A1 N1 T1 A5 The outputs of this register bit will not be suspended by the DCS# and CSR# Control The outputs of this register bit will not be suspended by the DCS# and CSR# Control Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control
B5, C5
B5, C5
B5, C5 D5
Q5A, 6A, 8A, E5, F5, K5, L5, M5 9A, 10A Q11A N5
E5, F5, K5, L5, M5 E5, F5, K5, L5, M5 Data Outputs that are suspended by the DCS# and CSR# control N5
Rev 1.0, November 25, 2006
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CY2SSTU32864
Pin Definitions (continued)
Pin Name Q14A Q1B Q2B-3B Q4B Q5B, 6B, 8B, 9B, 10B, Q11B Q12B, 13B Q14B Q15-25 QCSA# QCSB# QODTA QODTB QCKEA QCKEB NC A5 D5 B6, C6, E6, F6, K6, L6, M6, N6, P6, R6, T6 H5 H5 H6 D5 D6 A5 A6 H5 H6 N5 N6 T5 T6 B6, C6 T5 Pin Number (C0 = 0, C1 = 0) Pin Number (C0 = 0, C1 = 1) P5, R5 T5 A6 B6, C6 D6 Pin Number (C0 = 1, C1 = 1) P5, R5 Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control Description
Q12A, Q13A P5, R5
E6, F6, K6, L6, M6 E6, F6, K6, L6, M6 Data Outputs that are suspended by the DCS# and CSR# control N6 P6, R6 T6 P6, R6 Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control Data Outputs that are suspended by the DCS# and CSR# control Data outputs that will not be suspended by the DCS# and CSR# control Data outputs that will not be suspended by the DCS# and CSR# control Data outputs that will not be suspended by the DCS# and CSR# control Data outputs that will not be suspended by the DCS# and CSR# control Data outputs that will not be suspended by the DCS# and CSR# control Data outputs that will not be suspended by the DCS# and CSR# control
A2, A6, D2, D6, G1, H6 A2, B2, C2, D2, A2, B2, C2, D2, No Connect Pins E2, F2, G1, K2, L2, E2, F2, G1, K2, L2, M2, N2, P2, R2, T2 M2, N2, P2, R2, T2
Rev 1.0, November 25, 2006
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CY2SSTU32864
Table 1. Flip Flop Function Table Inputs RESET# H H H H H H H H H H H H L DCS# L L L L L L H H H H H H CSR# L L L H H H L L L H H H L or H L or H X or Floating L or H L or H L or H L or H L or H L or H CK CK# Dn, DODT, DCKE L H X L H X L H X L H X X or Floating Qn L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L Outputs QCS# L L Q0 L L Q0 H H Q0 H H Q0 L QODT, QCKE L H Q0 L H Q0 L H Q0 L H Q0 L
X or Floating X or Floating X or Floating
Rev 1.0, November 25, 2006
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CY2SSTU32864
Absolute Maximum Conditions [1]
Parameter VIN VOUT TS VCC IIK IOK IO Description Input Voltage Range
[2, 3]
Condition
Min. -0.5 -0.5 -65 -0.5
Max. VDD + 0.5 VDD + 0.5 150 2.5 50 50 50 100
Unit V V C V mA mA mA mA
Output Voltage Range[2, 3] Storage Temperature Supply Voltage Range Input Clamp Current Output Clamp Current Continuous Output Current Continuous Current through VDD/GND VO < 0 or VO > VDD VO < 0 or VO > VDD VO = 0 to VDD
-50 -50 -50 -100
DC Electrical Specifications
Parameter TA VDD VICR VID VREF VTT VI II VIL VIH VOL VOH IOH IOL IDD Description Ambient Operating Temp Operating Voltage Input Differential Common CK, CK# Mode Voltage Range Input Differential Voltage Voltage Reference Terminating Voltage Input Voltage Input Current AC Input Low Voltage DC Input Low Voltage AC Input High Voltage DC Input High Voltage Output Low Voltage Output High Voltage Output High Current Output Low Current Static Standby Power Supply Current Static Operating Power Supply Current RESET# = GND, IO = 0, VDD = 1.9V RESET# = VDD, VI = VIH(AC) or VIL(AC), IO = 0, VDD = 1.9V VI = VDD or GND Data Inputs Data Inputs Data Inputs Data Inputs IOL = 100 A, VCC = 1.7V to 1.9V IOL = 6 mA, VCC = 1.7V IOH = -100 A, VCC = 1.7V to 1.9V IOH = -6 mA, VCC = 1.7V CK, CK# Conditions Min. 0 1.7 0.675 600 0.49*VDD 0 -5 - - VREF + 250 mV VREF + 125 mV - - VDD - 0.2 1.2 - - Max. 70 1.9 1.125 - 0.51*VDD VDD 5 VREF - 250 mV VREF - 125mV - - 0.2 0.5 - - -8 8 100 40 Unit C V V mV V V V A V V V V V V V V mA mA A mA
VREF - 40 mV VREF + 40 mV
Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stresses ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 2.5V (max.)
Rev 1.0, November 25, 2006
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CY2SSTU32864
DC Electrical Specifications (continued)
Parameter IDDD Description Conditions Min. Max. 28 (typical) Unit A/MHz RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, Power Supply Current Dynamic Operating Clock CK# switching 50% duty cycle, Only VDD = 1.8V Dynamic Operating per each Data Input RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:1 configuration RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:2 configuration Low Power Active Mode, CLK only Low Power Active Mode per each Data Input RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, CS Enabled RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:1 configuration, CS Enabled RESET# = VDD, VI = VIH(AC) or VIL(AC), CK, CK# switching 50% duty cycle, VDD = 1.8V, 1 IO switching 1:2 configuration; CS Enabled CIN Ci (Data) Ci (CK and CK#) Ci (RESET#) VI = VREF 250 mV VIX = 0.9V, VID = 600 mV VI = VDD or GND 2.5 2 2.5
18 (typical)
A/MHz
36 (typical)
A/MHz
27 (typical)
A/MHz
2 (typical)
A/MHz
2 (typical)
A/MHz
3.5 3
pF pF pF
AC Timing Specifications
Parameter FCLK TW TACT[4,5] TINACT[4,5] TSU Description Clock Frequency Pulse Duration Differential Input Active Time Differential Input Inactive Time Set up Time DCS# before crossing CK,CK#, CSR = H, CK going high DCS# before crossing CK,CK#, CSR = L, CK going high CSR, ODT, CKE and data before crossing CK,CK#, CK going high TH Hold Time DCS#, CSRT#, ODT, CKE and data after crossing CK,CK#, CK going high From CK, CK# to Q From CK, CK# to Q - simultaneous switching RESET# Start to Q Low dv/dt_r (20 to 80%) dv/dt_f (20 to 80%) 1 1 - CK,CK# H or L Conditions Min. - 1 - - 0.7 0.5 0.5 Max. 500 - 10 15 - - - Unit MHz ns ns ns ns ns ns
0.5
-
ns
TPDM TPDMS TrPHL SLR dv/dt
Propagation Delay without Switching Propagation Delay with Switching Propagation Delay from High to Low Slew Rate Rising Slew Rate Falling Delta between Rising/Falling Rates
1.86 1.87 3 4 4 1
ns ns ns V/ns V/ns V/ns
Notes: 4. Data and VREF inputs must be low a minimum time of TACT max, after RESET# is taken high. 5. Data, VREF and clock inputs must be held at valid levels (not floating) a minimum time of TINACT max after RESET# is taken low.
Rev 1.0, November 25, 2006
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CY2SSTU32864
DUT TL = 350ps, 50 CL = 30pF
VDD RL = 1000
CK Inputs Test Point RL = 100 Test Point
CK CK
OUT
Test Point RL = 1000
Note: CL includes probe and jig capacitance
Figure 1. Test Load for Timing Measurements #1
DUT
VDD RL = 50 OUT CL = 10pF Test Point
Figure 2. Slew Rate Measurement Load High to Low
DUT
OUT CL = 10pF
Test Point
Figure 3. Slew Rate Measurement Load Low to High
RESET VDD/2 Input D 50% VDD/2
tinact
tact
Figure 4. Active and Inactive Times
tw Input VICR VICR VID
Figure 5. Pulse Duration
Rev 1.0, November 25, 2006
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CY2SSTU32864
CK VICR CK tsu Input VREF th VIH VREF VIL VID
Figure 6. Set-up and Hold Times
CK VICR CK tPLH Output VTT tPHL VTT VOH VOL VICR VID
Figure 7. Propagation Delay
RESET# VDD/2 tRPHL VOH Output VTT VOL VIH VIL
Figure 8. Propagation Delay after RESET#
Rev 1.0, November 25, 2006
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CY2SSTU32864
Ordering Information
Part Number CY2SSTU32864BFXC CY2SSTU32864BFXCT 96-pin FBGA 96-pin FBGA- Tape and Reel Package Type Product Flow Commercial, 0 to 85C Commercial, 0 to 85C
Package Drawing and Dimensions
96 FBGA (5.5 x 13.5 x 1.2 mm) BA96A
TOP VIEW A1 CORNER BOTTOM VIEW A1 CORNER 1 A B C D 6.00 E F G 13.500.10 H J K L M 0.80 N P R T 13.500.10 12.00 2 3 4 5 6 6 5 4 3 2 1 A B C D E F G H J K L M N P R T O0.05 M C O0.25 M C A B O0.500.05(96X)
DIMENSIONS IN MILLIMETERS REFERENCE JEDEC MO-205 PKG. WEIGHT: 0.23 gms PART # BF96A STANDARD PKG. BP96A LEAD FREE PKG.
A B 5.500.10
A
2.00 0.80
0.530.05
4.00 0.400.05 0.15 C
0.25 C
B 0.15(4X) SEATING PLANE 0.26 C 1.20 MAX
5.500.10
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 25, 2006
Page 9 of 9

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